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As text on Substack: p
Twitter thread: 6
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Video chapters:
00:00 – Intro and rambling
02:18 – Die sizes and transistor density
03:56 – AD102 floorplan interpretation
04:45 – N31 floorplan interpretation
05:38 – Area breakdown of N31 and AD102 (+AD103 floorplan)
08:29 – Rough cost per die calculations
12:32 – Monolithic 5 nm N31 chip size and cost estimate (384b)
14:20 – Monolithic 5 nm N31 chip size and cost estimate (256b)
17:38 – N31 respin talks
18:52 – Performance per mm² view
20:22 – Outro, Goodbye!
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Used sources:
Small Raptor image by Mehmet Turgut Kirkgoz on Pexels:
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TSVs for extra cache on the MCDs claim by Angstronomics:
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Performance and performance per watt analysis by 3DCenter.org for N31 and AD102/103 products:
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AD102/103 die shots from TechAnalyE via Twitter:
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Fiddler on the Roof (1/10) Movie CLIP – Tradition! (1971) HD:
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Ian Cutress / TechTechPotato 5/6/7 nm wafer prices:
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Wafer prices from The Information Network via Robert Castellano/Seekingalpha:
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Cerebras Wafer Scale Engine image:
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Projected defect density for N5 by TSMC via Anandtech: 5
Die per wafer calculator via:
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Performance and power consumption numbers for the GF100/GF110 GPU chips from Computerbase:
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Football image by Riccardo on Pexels:
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